Delay of general adders is determined by carry propagation paths. In order to increase the operating speed of an adder, the carry propagation paths are reduced by using a Background Art carry look-ahead adder (CLA) which includes Manchester carry chains. Such a CLA according to the Background Art that generates carry propagation bits and carry generation bits for two operators with binary values to be summed, e.g., an addend and an augend, and then calculates final summation values from bit carries selected by block carry signals. Such a CLA is disclosed in U.S. Pat. No. 5,508,952 or Japanese Patent Publication No. 1993-61643.
More specifically, the Background Art CLA calculates block carry signals and bit carries using the carry propagation bits and the carry generation bits generated at rising edges of a predetermined clock signal indicating the start of a summation operation, e.g., at those times that the clock signal transitions to an active state. However, instead of calculating the final summation values in one phase within the active period of the clock signal, the Background Art CLA calculates the final summation values from the bit carries when a predetermined enable signal is activated in synchronization with falling edges of the clock signal, e.g., when a sense amplifier flip-flop (F/F) is driven in a next phase in the active period of the clock signal.
Accordingly, the moment when the block carry signals are generated according to the Background Art CLA varies depending on the size of the addend and the augend. Thus, a timing margin (via an enabling clock signal) is introduced before a summation of all bits is performed to accommodate delay associated with large addends and/or augends. In other words, although carries are generated and propagated during the active state of the clock signal after a rising edge, operation of the sense amplifier F/F is delayed until the next phase of the clock signal to accommodate variable sizes of the addends and/or augends.